An A/D converter of the oversampling type is one in which the analog input voltage is sampled at a rate that is substantially higher than the desired output sampling rate of the converter. Converters of this type are well known in the art and typically have an oversampling front end quantizer and a digital decimation filter which processes the output of the front end quantizer. A suitable front-end quantizer for this purpose is the delta-sigma modulator, which is also referred to in the literature as a sigma-delta modulator.
A typical A/D converter of the oversampling type is illustrated in FIG. 1 and is generally indicated by the reference numeral 10. The prior art A/D converter 10 includes a delta-sigma modulator 12 having an output labeled DFAST which is coupled to the input of a digital decimation filter 14. The delta-sigma modulator 12 includes a switched capacitor integrator 16 which receives the analog input at an analog input node 18. The output of the switched capacitor integrator 16 is coupled to one input of a clocked comparator 20, the other input of which is coupled to ground. The output of the clocked comparator 20 provides a signal designated as SELECT. The signal SELECT is used in a feedback loop to determine whether a positive effective feedback voltage reference VREF+ or a negative effective feedback voltage reference VREF- is to be fed back into the switched capacitor integrator 16. In conventional A/D converters of the oversampling type, the positive effective feedback voltage reference is made to have a value that is equal to the specified maximum positive analog input voltage, and the effective negative feedback voltage reference is made to have a value that is equal to the specified maximum negative analog input voltage. See, for example, Hauser, M. W., Hurst, P. J., Brodersen, R. W., "MOS ADC-Filter Combination That Does Not Require Precision Analog Components," ISSCC Digest of Technical Papers, pp. 80-81, 313; Feb., 1985. Also see, for example, FIG. 3 and the discussion thereof in Everard, J. D., "A Single-Channel PCM Codec," IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 1, pp. 25-37; Feb., 1979.
The output of the clocked comparator 20 is coupled through a buffer 22 to provide the signal DFAST to the digital decimation filter 14. The theory and operation of delta-sigma modulators is well known to those of ordinary skill in the art, and, therefore, will not be discussed here in detail. For the present purposes, it should suffice to note that the output DFAST is a continuous high-speed digital bit pattern 11. The digital bit pattern is clocked at the same frequency as that at which the analog input node 18 is sampled. A typical clock rate is 2.048 MHz; this rate is substantially higher than the frequencies of interest applied to the analog input node 18. For a typical application, the frequencies of interest at the analog input node 18 are from DC to approximately 8 kHz. For a given number of samples of the analog input node 18--384 samples, for example--the relative number of logic 1's to logic 0's which are output from the delta-sigma modulator 12 and which comprise the signal DFAST is indicative of the polarity and magnitude of the voltage being applied to the analog input node 18.
It is a function of the digital decimation filter 14 to extract the low frequency analog voltage input information which is embedded in the high-speed serial bit stream being outputted from the delta-sigma modulator 12, and to provide a 16-bit digital representation of that sampled analog input. Another function of the digital decimation filter 14 is to provide a low-pass frequency response for the incoming analog signal. The 16-bit digital output samples are outputted at a much lower rate than that at which the analog input node 18 is sampled by the delta-sigma modulator 12. In the prior art A/D converter 10, it is conventional to internally utilize a large number of predetermined multi -bit digital codes, called impulse-response coefficients, in the convolution process performed by the digital decimation filter 14. See, for example, the above-referenced Hauser article at page 80 and the above-referenced Everard article at page 28. These impulse-response coefficients and the use thereof are further discussed hereinbelow in the Description of a Preferred Embodiment.
Referring now to FIG. 2, for the prior art A/D converter 10, there is illustrated a diagram of noise in the 16-bit digital output as a function of the DC level applied to the analog input node 18. The diagram of FIG. 2 may be constructed in the following manner. A DC voltage is applied to the analog input node 18 while a large number (1000, for example) of the 16-bit digital output codes are recorded. The variation of these digital output codes around an average value is defined as noise. The plot in FIG. 2 of this noise as a function of the DC level of the analog input voltage shows that the noise greatly increases when the analog input voltage approaches either the positive effective voltage reference or the negative effective voltage reference. The plot of FIG. 2 is representative of a second order modulator; for this case, the noise is not appreciable until the magnitude of the DC level of the analog input voltage becomes greater than 8/10 of the effective reference voltage.
In accordance with the foregoing, a need exists for a method for reducing the output noise of an A/D converter of the oversampling type, and particularly with respect to analog input signals having DC levels that approach the specified maximum input voltage limits. Additionally, a need exists for circuitry which may economically be used in conjunction with such method.